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? 1. general description the DAC1627D1G25 is a high-speed 16-bit du al channel digital-to-analog converter (dac). it incorporates selectable ? 2, ? 4 and ? 8 interpolation filters optimized for multi-carrier and broadband wireless transmitters at sample rates of up to 1.25 gsps. the DAC1627D1G25 is supplied by two power supp lies and integrates a differential scalable output current up to 34 ma. the DAC1627D1G25 meets multi-carrier global system for mobile communications (gsm) specifications. for example, with an nco frequency of 153.6 mhz and a dac clock frequency of 1.2288 gsps the full-scale dynamic range is: ? sfdr rbw = 91 dbc (bandwidth = 180 mhz) ? imd3 = 85 dbc the serial peripheral interface (spi) prov ides full control of the DAC1627D1G25. the DAC1627D1G25 integrates a low voltage dif ferential signaling (lvds) double data rate (ddr) receiver interf ace, with an on-chip 100 ? termination. the lvds ddr interface accepts a multiplex input data stream such as interleaved or folded. an internal lvds input auto-calibration ensures the ro bustness and stabilit y of the interface. digital on-chip modulation converts the complex i and q inputs from baseband to if. a 40-bit numerically controlled oscillator (nco) sets the mixe r frequency. high resolution internal gain, phase and offset control provide outsta nding image and local oscillator (lo) signal rejection at the system analog modulator output. an inverse (sin x) / x function ensures a cont rolled flatness 0.5 db for high bandwidths at the dac output. multiple device synchronizatio n (mds) allows synchronization of the outputs of multiple dac devices. mds guarantees a maximum sk ew of one output clock period between several devices. the DAC1627D1G25 includes a low noise capa citor-free integrated phase-locked loop (pll) multiplier which generates a dac clock rate from the lvds clock rate. the DAC1627D1G25 is available in an hvqfn72 package (10 mm ? 10 mm). DAC1627D1G25 dual 16-bit dac, lvds interface, up to 1.25 gsps, x2, x4 and x8 interpolating rev. 03 ? 2 july 2012 data sheet
DAC1627D1G25 3 ? idt 2012. all rights reserved. data sheet rev. 03 ? 2 july 2012 2 of 81 integrated device technology DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating 2. features and benefits 3. applications ? wireless infrastructure: mc_gsm, lte, wimax, gsm, cdma, wcdma, td-scdma ? communications: lmds/mmds, point-to-point ? direct digital synthesis (dds) ? digital radio links ? instrumentation ? automated test equipment (ate) 4. ordering information ? dual-channel 16-bit resolution ? synchronization of multiple dac devices ? 1.25 gsps maximum update rate ? 3-wire or 4-wire mode spi interface ? selectable ? 2, ? 4 and ? 8 interpolation filters ? differential scalable output current from 8.1 ma to 34 ma ? low noise capacitor-free integrated phase-locked loop (pll) ? external analog offset control (10-bit auxiliary dacs) ? embedded numerically controlled oscillator (nco) with 40-bit programmable frequency ? high resolution internal digital gain and offset control to support high performance iq-modulator image rejection ? embedded complex (i/q) modulator ? internal phase correction ? two power supplies ? inverse (sin x) / x function ? lvds ddr compatible input interface with on-chip 100 ? terminations ? power-down mode and sleep mode; 5-bit nco low-power mode ? lvds ddr input clock up to 400 mhz ? on-chip 1.25 v reference ? lvds or lvpecl compatible dac clock ? industrial temperature range ? 40 ? c to +85 ? c ? interleaved or folded i and q data input mode ? 72 pins small form factor hvqfn package table 1. ordering information type number package name description version DAC1627D1G25 hvqfn72 plastic thermal enhanced very thin quad flat package; no leads; 72 terminals; body 10 ? 10 ? 0.85 mm sot813-3 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx DAC1627D1G25 3 ? idt 2012. all rights reserved. data sheet rev. 03 ? 2 july 2012 3 of 81 integrated device technology DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating 5. block diagram fig 1. block diagram 001aan827 ioutbp ioutbn ioutap ioutan auxap auxan sin cos + offset control dac b x sin x gapout vires + x sin x 10-bit analog gain control 10-bit analog gain control clipping clipping 10-bit offset control nco 40-bit frequency setting 16-bit phase adjustment 10-bit offset control ref. bandgap and biasing dac a aux. dac auxbp auxbn aux. dac x2 fir 2 x2 fir 1 multi-dac synchronization x2 fir 2 x2 fir 3 x2 fir 3 x2 fir 1 clock generator/pll dcmsu cdi spi sdo sdio scs_n sclk mds coarse phase compensation digital gain/offset lvds ddr/ dif clkp ldclkn ldclkp ld(15)n to ld(0)n ld(15)p to ld(0)p alignn alignp clkn mdsp mdsn interrupt internal monitoring io1 io0 reset_n dac1627d complex modulator + + + - 16 16 DAC1627D1G25 3 ? idt 2012. all rights reserved. data sheet rev. 03 ? 2 july 2012 4 of 81 integrated device technology DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating 6. pinning information 6.1 pinning 6.2 pin description fig 2. pin configuration 001aan828 DAC1627D1G25 transparent top view ld[4]n ld[12]n ld[11]p ld[3]p ld[12]p ld[3]n ld[13]n ld[2]p ld[13]p ld[2]n v ddd v ddd ld[14]n ld[1]p ld[14]p ld[1]n ld[15]n ld[0]p ld[15]p ld[0]n alignn io1 alignp io0 tm sdo mdsn sdio mdsp sclk clkn scs_n ld[10]p ld[10]n ld[9]p ld[9]n ld[8]p ld[8]n v ddd lckp lckn n.c. ld[7]p ld[7]n ld[6]p ld[6]n ld[5]p ld[5]n ioutan ioutap v dda(1v8)_d v dda(3v3) auxap auxan v dda(1v8)_p2 gapout vires v dda(1v8)_p1 auxbn auxbp v dda(3v3) v dda(1v8)_d ioutbp ioutbn ld[11]n ld[4]p clkp reset_n v ddd v ddd v dda(1v8)_d v dda(1v8)_d 17 18 38 37 16 39 15 40 14 41 13 42 12 43 11 44 10 45 9 46 8 47 7 48 6 49 5 50 4 51 3 52 2 1 53 54 71 72 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 20 19 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 terminal 1 index area table 2. pin description symbol pin type [1] description clkp 1 i dac clock positive input clkn 2 i dac clock negative input mdsp 3 io multi-device synchro nization positive signal mdsn 4 io multi-device synchronization negative signal tm 5 i test mode selection (connect to gnd) alignp 6 i positive input for data alignment alignn 7 i negative input for data alignment ld[15]p 8 i lvds positive input bit 15 [2] ld[15]n 9 i lvds negative input bit 15 [2] DAC1627D1G25 3 ? idt 2012. all rights reserved. data sheet rev. 03 ? 2 july 2012 5 of 81 integrated device technology DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating ld[14]p 10 i lvds positive input bit 14 [2] ld[14]n 11 i lvds negative input bit 14 [2] v ddd 12 p digital power supply ld[13]p 13 i lvds positive input bit 13 [2] ld[13]n 14 i lvds negative input bit 13 [2] ld[12]p 15 i lvds positive input bit 12 [2] ld[12]n 16 i lvds negative input bit 12 [2] ld[11]p 17 i lvds positive input bit 11 [2] ld[11]n 18 i lvds negative input bit 11 [2] v ddd 19 p digital power supply ld[10]p 20 i lvds positive input bit 10 [2] ld[10]n 21 i lvds negative input bit 10 [2] ld[9]p 22 i lvds positive input bit 9 [2] ld[9]n 23 i lvds negative input bit 9 [2] ld[8]p 24 i lvds positive input bit 8 [2] ld[8]n 25 i lvds negative input bit 8 [2] v ddd 26 p digital power supply lckp 27 i lvds positive data clock input lckn 28 i lvds negative data clock input n.c. 29 - not connected ld[7]p 30 i lvds positive input bit 7 [2] ld[7]n 31 i lvds negative input bit 7 [2] ld[6]p 32 i lvds positive input bit 6 [2] ld[6]n 33 i lvds negative input bit 6 [2] ld[5]p 34 i lvds positive input bit 5 [2] ld[5]n 35 i lvds negative input bit 5 [2] v ddd 36 p digital power supply ld[4]p 37 i lvds positive input bit 4 [2] ld[4]n 38 i lvds negative input bit 4 [2] ld[3]p 39 i lvds positive input bit 3 [2] ld[3]n 40 i lvds negative input bit 3 [2] ld[2]p 41 i lvds positive input bit 2 [2] ld[2]n 42 i lvds negative input bit 2 [2] v ddd 43 p digital power supply ld[1]p 44 i lvds positive input bit 1 [2] ld[1]n 45 i lvds negative input bit 1 [2] ld[0]p 46 i lvds positive input bit 0 [2] ld[0]n 47 i lvds negative input bit 0 [2] io1 48 io io port bit 1 io0 49 io io port bit 0 sdo 50 o spi data output table 2. pin description ?continued symbol pin type [1] description DAC1627D1G25 3 ? idt 2012. all rights reserved. data sheet rev. 03 ? 2 july 2012 6 of 81 integrated device technology DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating [1] p: power supply; g: ground; i: input; o: output. [2] the lvds input data bus order can be reversed and each element can be swapped between p and n using dedicated registers (see table 60). 7. limiting values sdio 51 io spi data input/output sclk 52 i spi clock scs_n 53 i spi chip se lect (active low) reset_n 54 i general reset (active low) v dda(1v8)_d 55 p 1.8 v analog power supply (dac core) ioutbn 56 o complementary dac b output current ioutbp 57 o dac b output current v dda(1v8)_d 58 p 1.8 v analog power supply (dac core) v dda(3v3) 59 p 3.3 v analog power supply auxbp 60 o auxiliary dac b output current auxbn 61 o complementary auxiliary dac b output current v dda(1v8)_p1 62 p 1.8 v analog power supply (pll) vires 63 io dac biasing resistor gapout 64 io band gap input/output voltage v dda(1v8)_p2 65 p 1.8 v analog power supply (pll) auxan 66 o complementary auxiliary dac a output current auxap 67 o auxiliary dac a output current v dda(3v3) 68 p 3.3 v analog power supply v dda1v8_d 69 p 1.8 v analog power supply (dac core) ioutap 70 o dac a output current ioutan 71 o complementary dac a output current v dda(1v8)_d 72 p 1.8 v analog power supply (dac core) gnd h g ground (exposed die pad) table 2. pin description ?continued symbol pin type [1] description table 3. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v dda(3v3) analog supply voltage (3.3 v) ? 0.5 +4.6 v v ddd digital supply voltage ? 0.5 +2.5 v v dda(1v8) analog supply voltage (1.8 v) [1] ? 0.5 +2.5 v v i input voltage input pins referenced to gnd ? 0.5 +2.5 v v o output voltage pins ioutap, ioutan, ioutbp, ioutbn, auxap, auxan, auxbp and auxbn referenced to gnd ? 0.5 +4.6 v DAC1627D1G25 3 ? idt 2012. all rights reserved. data sheet rev. 03 ? 2 july 2012 7 of 81 integrated device technology DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating [1] connect the analog 1.8 v power supply to pins vdda1v8_d, vdda1v8_p1, and vdda1v8_p2. 8. thermal characteristics [1] value for six-layer board in still ai r with a minimum of 49 thermal vias. t stg storage temperature ? 55 +150 ? c t amb ambient temperature ? 40 +85 ? c t j junction temperature ? 40 +125 ? c table 3. limiting values ?continued in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit table 4. thermal characteristics symbol parameter conditions typ unit r th(j-a) thermal resistance from junction to ambient [1] 16.2 k/w r th(j-c) thermal resistance from junction to case [1] 6.7 k/w DAC1627D1G25 3 ? idt 2012. all rights reserved. data sheet rev. 03 ? 2 july 2012 8 of 81 integrated device technology DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating 9. characteristics table 5. characteristics v dda(1v8) =1.8v; v ddd =1.8v; v dda(3v3) = 3.3 v; typical values measured at t amb =+25 ? c; r l =50 ? ; i o(fs) =20ma; maximum sample rate used; external pll; no auxiliary dac; no inverse sinus x/x; no output correction; output load condition defined in figure 42; output level = 1 v (p-p). symbol parameter conditions test [1] min typ max unit v dda(3v3) analog supply voltage (3.3 v) c 3.15 3.3 3.45 v v ddd digital supply voltage c 1.7 1.8 1.9 v v dda(1v8) analog supply voltage (1.8 v) c [2] 1.7 1.8 1.9 v i dda(3v3) analog supply current (3.3 v) auxiliary dac on c 51 55 59 ma i ddd digital supply current f s = 983.04 67; ? 4 interpolation; no nco; mds off c 475 525 585 ma f s =620msps; ? 2 interpolation; nco on; no mds c 400 450 500 ma i dda(1v8) analog supply current (1.8 v) f s = 983.04 msps; 1 v (p-p) c [2] 207 218 230 ma f s = 620 msps; 1 v (p-p) c 207 218 230 ma p tot total power dissipation f s = 1228.8 msps; ? 4 interpolation; 5-bit nco; mds off c - 1730 - mw f s = 983.04 msps; ? 4 interpolation; 5-bit nco; mds off c - 1580 - mw f s = 983.04 msps; ? 4 interpolation; nco off; mds off c - 1500 - mw f s =620msps; ? 2 interpolation; 5-bit nco; mds off -1370- mw power-down using spi register c- 63 - mw clock inputs (pins clkp, clkn) v i(clk)dif differential clock input voltage peak-to-peak c 150 - 1000 mv r i input resistance d- 200- k ? c i input capacitance d- 1 - pf DAC1627D1G25 3 ? idt 2012. all rights reserved. data sheet rev. 03 ? 2 july 2012 9 of 81 integrated device technology DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating digital inputs (pins ld[15]p to ld[0]p, ld[15]n to ld[0]n, lckp and l ckn, alignp and alignn) v i input voltage ? v gpd ? <50mv [3] c 825 - 1575 mv v idth input differential threshold voltage ? v gpd ? <50mv [3] c ? 100 - +100 mv r i input resistance d- 100- ? c i input capacitance d - 0.8 - pf pins lckp and lckn d - 0.9 - pf digital inputs/outputs (pins mdsn, mdsp) v o(dif)(p-p) peak-to-peak differential output voltage c- 500- mv c i input capacitance between gnd and pin mdsn or mdsp d - 0.6 - pf r i input resistance d- 100- ? v i input voltage ? v gpd ? <50mv [3] c 825 - 1575 mv v idth input differential threshold voltage ? v gpd ? <50mv [3] c ? 100 - +100 mv digital inputs/outputs (pins io0, io1 , sdo, sdio, sclk , scs_n, reset_n) v il low-level input voltage cgnd- 0.3v ddd v v ih high-level input voltage c0.7v ddd -v ddd v v ol low-level output voltage pins io0, io1, sdo, and sdio cgnd- 0.1v ddd v v oh high-level output voltage pins io0, io1, sdo, and sdio c0.9v ddd -v ddd v i il low-level input current maximum v il i ? 10 - +10 ? a i ih high-level input current minimum v ih i ? 10 - +10 ? a c i input capacitance d - 2.2 - pf analog outputs (pins iout ap, ioutan, ioutbp, ioutbn) i bias bias current dc current d - 2.5 - ma table 5. characteristics ?continued v dda(1v8) =1.8v; v ddd =1.8v; v dda(3v3) = 3.3 v; typical values measured at t amb =+25 ? c; r l =50 ? ; i o(fs) =20ma; maximum sample rate used; external pll; no auxiliary dac; no inverse sinus x/x; no output correction; output load condition defined in figure 42; output level = 1 v (p-p). symbol parameter conditions test [1] min typ max unit DAC1627D1G25 3 ? idt 2012. all rights reserved. data sheet rev. 03 ? 2 july 2012 10 of 81 integrated device technology DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating i o(fs) full-scale output current controlled by the analog gain registers (see table 33) d8.1 - 34 ma default value d - 20 - ma v o output voltage compliance range d 2.3 - v dda(3v3) v v o(cm) common-mod e output voltage 1 v (p-p) dac output configuration d- 3 - v 2 v (p-p) dac output configuration d- 2.8 - v r o output resistance d- 250- k ? c o output capacitance between pins outan and outbn and pins outap and outbp d- 5 - pf ? e o offset error variation i o(iout) =i o(fs) / 2 d - DAC1627D1G25 3 ? idt 2012. all rights reserved. data sheet rev. 03 ? 2 july 2012 11 of 81 integrated device technology DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating t sk(clk-d) skew time from clock to data input f data = 184.32 mhz c 800 - 830 ps f data = 245.76 mhz c 500 - 675 ps f data = 307.2 mhz c 300 - 520 ps f data = 368.64 mhz c 150 - 500 ps t su set-up time manual tuning mode (see figure 29); depends on ldclk_del[3:0] 0000 c ? 300 - - ps 0001 c ? 365 - - ps 0010 c ? 440 - - ps 0011 c ? 520 - - ps 0100 c ? 590 - - ps 0101 c ? 675 - - ps 0110 c ? 750 - - ps 0111 c ? 830 - - ps 1000 c ? 845 - - ps 1001 c ? 845 - - ps 1010 c ? 1000 - - ps 1011 c ? 1100 - - ps 1100 c ? 1220 - - ps 1101 c ? 1290 - - ps 1110 c ? 1360 - - ps 1111 c ? 1450 - - ps table 5. characteristics ?continued v dda(1v8) =1.8v; v ddd =1.8v; v dda(3v3) = 3.3 v; typical values measured at t amb =+25 ? c; r l =50 ? ; i o(fs) =20ma; maximum sample rate used; external pll; no auxiliary dac; no inverse sinus x/x; no output correction; output load condition defined in figure 42; output level = 1 v (p-p). symbol parameter conditions test [1] min typ max unit DAC1627D1G25 3 ? idt 2012. all rights reserved. data sheet rev. 03 ? 2 july 2012 12 of 81 integrated device technology DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating t hold hold time manual tuning mode (see figure 28); depends on ldclk_del[3:0]: 0000 c 790 - - ps 0001 c 870 - - ps 0010 c 950 - - ps 0011 c 1055 - - ps 0100 c 1140 - - ps 0101 c 1230 - - ps 0110 c 1360 - - ps 0111 c 1460 - - ps 1000 c 1900 - - ps 1001 c 2075 - - ps 1010 c 2250 - - ps 1011 c 2400 - - ps 1100 c 2560 - - ps 1101 c 2740 - - ps 1110 c 2900 - - ps 1111 c 3000 - - ps dac output timing f s(max) maximum sampling rate c 1250 - - msps t s settling time to ?? 0.5 lsb d - 20 - ns internal pll timing f s sampling rate d 50 - 1000 msps 40-bit nco frequency range; f s = 1000 msps f nco nco frequency two?s complement coding register value = 8000000000h d- ? 500 - mhz register value = ffffffffffh d- ? 0.9095 - mhz register value = 0000000000h d- 0 - hz register value = 0000000001h d - +0.9095 - mhz register value = 7fffffffffh d - +499.99909 - mhz f step step frequency d - 0.9095 - mhz table 5. characteristics ?continued v dda(1v8) =1.8v; v ddd =1.8v; v dda(3v3) = 3.3 v; typical values measured at t amb =+25 ? c; r l =50 ? ; i o(fs) =20ma; maximum sample rate used; external pll; no auxiliary dac; no inverse sinus x/x; no output correction; output load condition defined in figure 42; output level = 1 v (p-p). symbol parameter conditions test [1] min typ max unit DAC1627D1G25 3 ? idt 2012. all rights reserved. data sheet rev. 03 ? 2 july 2012 13 of 81 integrated device technology DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating low-power nco frequency range; f s = 1000 mhz f nco nco frequency two?s complement coding register value = f8000000000h d- ? 500 - mhz register value = f8000000000h d- ? 31.25 - mhz register value = 00000000000h d- 0 - hz register value = 08000000000h d - +31.25 - mhz register value = 7fffffffffh d - +468.75 - mhz f step step frequency d- 31.25- mhz dynamic performance sfdr spurious-free dynamic range f data =184.32mhz; f s = 737.28 msps; bw = f s /2 f o =20mhz at ? 1 dbfs; i - 85.5 - dbc f data =245.76mhz; f s = 983.04 msps; bw = f s /2 f o =20mhz at ? 1dbfs i - 85.5 - dbc sfdr rbw restricted bandwidth spurious-free dynamic range f data =245.76mhz; f s = 983.04 msps; f o =147mhz bw = 100 mhz i - 90 - dbc bw = 180 mhz i - 91 - dbc f data =307.2mhz; f s = 1228.8 msps; f o = 158.6 mhz bw = 100 mhz i - 88 - dbc bw = 180 mhz i - 91 - dbc imd3 third-order intermodulati on distortion f data =245.76mhz; f s = 983.04 msps; f o1 =20mhz; f o2 =21mhz; ? 4 interpolation; output level = ? 1dbfs c- >95- dbc f data =245.76mhz; f s = 983.04 msps; f o1 = 152 mhz; f o2 = 155.1 mhz; ? 4 interpolation; output level = ? 1dbfs i- 85- dbc table 5. characteristics ?continued v dda(1v8) =1.8v; v ddd =1.8v; v dda(3v3) = 3.3 v; typical values measured at t amb =+25 ? c; r l =50 ? ; i o(fs) =20ma; maximum sample rate used; external pll; no auxiliary dac; no inverse sinus x/x; no output correction; output load condition defined in figure 42; output level = 1 v (p-p). symbol parameter conditions test [1] min typ max unit DAC1627D1G25 3 ? idt 2012. all rights reserved. data sheet rev. 03 ? 2 july 2012 14 of 81 integrated device technology DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating [1] d = guaranteed by design; c = guaranteed by c haracterization; i = 100 % industrially tested. [2] connect v dda(1v8)_d , v dda(1v8)_p1 and v dda(1v8)_p2 to the same 1.8 v analog power supply. use dedicated filters for the three power pins. [3] ? v gpd ? represents the ground potential difference voltage. this voltage is the result of current flowing through the finite resistanc e and the inductance between the receiver and the driver circuit ground voltages. acpr adjacent channel power ratio with wcdma pattern; f s = 1228.8 msps; ? 4 interpolation; f nco = 153.6 mhz 1 carrier; bw = 5 mhz c - 81.5 - dbc 2 carriers; bw = 10 mhz c - 76.5 - dbc 4 carriers; bw = 20 mhz c - 73 - dbc with wcdma pattern; f s = 983.04 msps; ? 4 interpolation; f nco =40mhz 4 carriers; bw = 20 mhz c - 73.5 - dbc nsd noise spectral density f s = 983.04 msps; ? 4 interpolation; f o =20mhzat ? 1dbfs d- ? 166 - dbm/hz f s = 983.04 msps; ? 4 interpolation; f o = 153.6 mhz at ? 1dbfs d- ? 164 - dbm/hz table 5. characteristics ?continued v dda(1v8) =1.8v; v ddd =1.8v; v dda(3v3) = 3.3 v; typical values measured at t amb =+25 ? c; r l =50 ? ; i o(fs) =20ma; maximum sample rate used; external pll; no auxiliary dac; no inverse sinus x/x; no output correction; output load condition defined in figure 42; output level = 1 v (p-p). symbol parameter conditions test [1] min typ max unit DAC1627D1G25 3 ? idt 2012. all rights reserved. data sheet rev. 03 ? 2 july 2012 15 of 81 integrated device technology DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating 10. typical characteristics typical measurement done at t amb = +25 c in typical power supply condition, i o(fs) = 20 ma, external pll, no auxiliary dac, no inverse (sinus x) / x, and no output correction. the output load condition defined in figure 42. all graphs are based on average measurements using several devices. (1) 0 dbfs (2) ? 7dbfs (3) ? 10 dbfs (1) 0 dbfs (2) ? 7dbfs (3) ? 10 dbfs fig 3. second harmonic distortion versus output frequency over input scale at f s = 983.04 mhz fig 4. second harmonic distortion versus output frequency over input scale at f s = 1228.8 mhz (1) 0 dbfs (2) ? 7dbfs (3) ? 10 dbfs (1) 0 dbfs (2) ? 7dbfs (3) ? 10 dbfs fig 5. third harmonic distortion versus output frequency over input scale at f s = 983.04 mhz fig 6. third harmonic distortion versus output frequency over input scale at f s = 1228.8 mhz d d d i r x w 0 + ] + g % f d d d i r x w 0 + ] + g % f i r x w 0 + ] d d d + g % f i r x w 0 + ] d d d + g % f DAC1627D1G25 3 ? idt 2012. all rights reserved. data sheet rev. 03 ? 2 july 2012 16 of 81 integrated device technology DAC1627D1G25 dual 16-bit dac: up to 1.25 gsps; x2, x4 and x8 interpolating (1) 0 dbfs (2) ? 7dbfs (3) ? 10 dbfs (1) 0 dbfs (2) ? 7dbfs (3) ? 10 dbfs fig 7. sfdr restricted bandwidth (200 mhz) versus output frequency over input scale at f s = 983.04 mhz fig 8. sfdr restricted bandwidth (200 mhz) versus output frequency over input scale at f s = 1228.8 mhz i r x w 0 + ] d d d 6 ) ' 5 u e z g % f i r x w 0 + ] d d d 6 ) ' 5 u e z g % f (1) -7 dbfs (2) -10 dbfs (3) -12 dbfs (1) -7 dbfs (2) -10 dbfs (3) -12 dbfs fig 9. imd3 versus output frequency over input scale at f s = 983.04 mhz fig 10. imd3 versus output frequency over input scale at f s = 1228.8 mhz i 1 & |